/**
  ******************************************************************************
  * @file    Libraries/Device/TS32Fx/ts32fx.h
  * @author  TOPSYS Application Team
  * @version V1.0.0
  * @date    02-11-2018
  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
  *          This file contains all the peripheral register's definitions, bits
  *          definitions and memory mapping for ts32fx Connectivity line.
  *          The file is the unique include file that the application programmer
  *          is using in the C source code, usually in main.c. This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripherals registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2018 TOPSYS</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 

/** @addtogroup CMSIS
  * @{
  */

/** @addtogroup TS32Fx
  * @{
  */

#ifndef __TS32FX_H
#define __TS32FX_H

#include <stdint.h>
#include "typedef.h"
#define    SBIT(n)  (1<<(n))
#define    CBIT(n) ~(1<<(n))

#ifdef __cplusplus
 extern "C" {
#endif


/** 
  * @brief  device defines  
  */
#define __CM0_REV                  0x0000U  /*!< Core Revision r2p0                           */
#define __NVIC_PRIO_BITS           2U       /*!< STM32 uses 4 Bits for the Priority Levels    */
#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */


/** @addtogroup Peripheral_registers_structures
  * @{
  */
     
/**
 * @brief TS32Fx Interrupt Number Definition, according to the selected device
 *        in @ref Library_configuration_section
 */
typedef enum IRQn {
/******  Cortex-M0 Processor Exceptions Numbers ***********************************************/
    NonMaskableInt_IRQn         = -14,      /*!< 2 Non Maskable Interrupt                     */
    HardFault_IRQn              = -13,      /*!< 3 Cortex-M0 Memory HardFault Interrupt       */
    MemoryManagement_IRQn       = -12,      /*!< 4 Cortex-M0 Memory Management Interrupt      */
    BusFault_IRQn               = -11,      /*!< 5 Cortex-M0 Bus Fault Interrupt              */
    UsageFault_IRQn             = -10,      /*!< 6 Cortex-M0 Usage Fault Interrupt            */
    SVCall_IRQn                 = -5,       /*!< 11 Cortex-M0 SV Call Interrupt               */
    DebugMonitor_IRQn           = -4,       /*!< 12 Cortex-M0 Debug Monitor Interrupt         */
    PendSV_IRQn                 = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt               */
    SysTick_IRQn                = -1,       /*!< 15 Cortex-M0 System Tick Interrupt           */

/******  specific Interrupt Numbers ***********************************************************/
    LVD_IRQn                    = 0,
    TKIRQ_IRQn                  = 1,
    TK_DONE_IRQn                = 2,
    TK_OVF_IRQn                 = 3,
    TK_OVT_IRQn                 = 4,
    UART0_IRQn                  = 5,
    UART1_IRQn                  = 6,
    //7,
    //8,  
    //9,
    SPI0_IRQn                   = 10,
    SPI1_IRQn                   = 11,
    GPIOA_IRQn                  = 12,
    GPIOB_IRQn                  = 13,
    GPIOC_IRQn                  = 14,
    WKPND_IRQn                  = 15,
    TIM0_IRQn                   = 16,
    TIM1_IRQn                   = 17,
    TIM2_IRQn                   = 18,
    TIM3_IRQn                   = 19,
    TIM4_IRQn                   = 20,
    TIM5_IRQn                   = 21,
    //22,
    //23,
    ADKEY_IRQn                  = 24,
    //25,
    //26,
    CRC_DMA_IRQn                = 27,
    COMP_IRQn                   = 28,
    WDT_IRQn                    = 29
    //30
    //31,
} IRQn_Type;

/**
  * @}
  */
#define ARM_MATH_CM0
#include "core_cm0.h" 

/** @addtogroup Peripheral_registers_structures
  * @{
  */

/*
typedef struct {
    __IO uint32_t CON;
    __IO uint32_t TAR;
    __IO uint32_t SAR;
    __IO uint32_t HS_MADDR;
    
    __IO uint32_t DATA_CMD;
    __IO uint32_t SS_SCL_HCNT;
    __IO uint32_t SS_SCL_LCNT;
    __IO uint32_t FS_SCL_HCNT;
    
    __IO uint32_t FS_SCL_LCNT;
    __IO uint32_t HS_SCL_HCNT;
    __IO uint32_t HS_SCL_LCNT;
    __IO uint32_t INTR_STAT;
    
    __IO uint32_t INTR_MASK;
    __IO uint32_t RAW_INTR_STAT;
    __IO uint32_t RX_TL;
    __IO uint32_t TX_TL;
    
    __IO uint32_t CLR_INTR;
    __IO uint32_t CLR_RX_UNDER;
    __IO uint32_t CLR_RX_OVER;
    __IO uint32_t CLR_TX_OVER;
    
    __IO uint32_t CLR_RD_REQ;
    __IO uint32_t CLR_TX_ABRT;
    __IO uint32_t CLR_RX_DONE;
    __IO uint32_t CLR_ACTIVITY;
    
    __IO uint32_t CLR_STOP_DET;
    __IO uint32_t CLR_START_DET;
    __IO uint32_t CLR_GEN_CALL;
    __IO uint32_t ENABLE;
    
    __IO uint32_t STATUS;
    __IO uint32_t TXFLR;
    __IO uint32_t RXFLR;
    __IO uint32_t SDA_HOLD;
    __IO uint32_t TX_ABRT_SOURCE;
    __IO uint32_t SLV_DATA_NACK_ONLY;
    __IO uint32_t DMA_CR;
    __IO uint32_t DMA_TDLR;
    __IO uint32_t DMA_RDLR;
    __IO uint32_t SDA_SETUP;
    __IO uint32_t ACK_GENERAL_CALL;
    __IO uint32_t ENABLE_STATUS;
    __IO uint32_t FS_SPKLEN;
    __IO uint32_t HS_SPKLEN;
    __IO uint32_t CLR_RESTART_DET;
    __IO uint32_t SCL_STUCK_AT_LOW_TIMEOUT;
    __IO uint32_t SDA_STUCK_AT_LOW_TIMEOUT;
    __IO uint32_t CLR_SCL_STUCK_DET;
    __IO uint32_t DEVICE_ID;
    __IO uint32_t SMBUS_CLOCK_LOW_SEXT;
    __IO uint32_t SMBUS_CLOCK_LOW_MEXT;
    __IO uint32_t SMBUS_THIGH_MAX_IDLE_COUNT;
    __IO uint32_t SMBUS_INTR_STAT;
    __IO uint32_t SMBUS_INTR_MASK;
    __IO uint32_t SMBUS_INTR_RAW_STATUS;
    __IO uint32_t CLR_SMBUS_INTR;
    __IO uint32_t OPTIONAL_SAR;
    __IO uint32_t SMBUS_UDID_LSB;
} IIC_TypeDef;
*/
/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
typedef struct
{
    __IO uint32_t CON;
    __IO uint32_t BAUD;
    __IO uint32_t DATA;
    __IO uint32_t STA;
    __IO uint32_t TSTADR;
    __IO uint32_t RSTADR;
    __IO uint32_t TDMALEN;
    __IO uint32_t RDMALEN;
    __IO uint32_t TDMACNT;
    __IO uint32_t RDMACNT;
    __IO uint32_t DMACON;
    __IO uint32_t RS485_CON;
    __IO uint32_t RS485_DET;
    __IO uint32_t RS485_TAT;
} UART_TypeDef;


/**
  * @brief Serial Peripheral Interface
  */
typedef struct
{
    __IO uint32_t CON0;
    __IO uint32_t CON1;
    __IO uint32_t CMD_DATA;
    __IO uint32_t BAUD;
    __IO uint32_t DMA_LEN;
    __IO uint32_t DMA_CNT;
    __IO uint32_t DMA_STADR;
    __IO uint32_t STA;
} SPI_I2C_TypeDef;

typedef struct
{
    __IO uint32_t CON0;
    __IO uint32_t STPRD0;
    __IO uint32_t STPRD1;
    __IO uint32_t RTPRD0;
    __IO uint32_t RTPRD1;
    __IO uint32_t ZPRD0;
    __IO uint32_t ZPRD1;
    __IO uint32_t OPRD0;
    __IO uint32_t OPRD1;
    __IO uint32_t TO;
    __IO uint32_t THD;
    __IO uint32_t DAT0;
    __IO uint32_t DAT1;
    __IO uint32_t CNT;
} IR_TypeDef;

/**
  * @brief WDT
  */
typedef struct
{
    __IO uint32_t WDTCON;
    __IO uint32_t WDTKEY;
} WDT_TypeDef;

/**
  * @brief Frac PLL 0
  */
typedef struct {
    __IO uint32_t FPLL_CON;
    __IO uint32_t FPLL_INT;
    __IO uint32_t FPLL_FRAC;
    __IO uint32_t FPLL_SSC;
} FPLL_TypeDef;

/**
  * @brief RTC
  */
//typedef struct
//{
//    __IO uint32_t RTCCON;
//    __IO uint32_t RTCCPND;
//    __IO uint32_t RTCSECCNT;
//    __IO uint32_t RTCDATA;
//} RTC_TypeDef;

/**
  * @brief TIMERs
  */
typedef struct
{
    __IO uint32_t TMR_CON;
    __IO uint32_t TMR_CNT;
    __IO uint32_t TMR_PR;
    __IO uint32_t TMR_PWM;
} TIMER_TypeDef;

/**
  * @brief TIMER5
  */
typedef struct
{
    __IO uint32_t TMR_CON;
    __IO uint32_t TMR_CNT;
    __IO uint32_t TMR_PR;
    __IO uint32_t TMR_PWM;
    __IO uint32_t TMR_PR0;
    __IO uint32_t TMR_PWM0;
    __IO uint32_t TMR_PR1;
    __IO uint32_t TMR_PWM1;
    __IO uint32_t TMR_BITCNT;
    __IO uint32_t TMR_TXDAT;
    __IO uint32_t TMR_IRSTA;
} TIMER5_TypeDef;

/**
  * @brief ADKEY
  */
typedef struct{
    __IO uint32_t CFG;
    __IO uint32_t CR;
    __IO uint32_t CHS;
    __IO uint32_t CHS1;
    __IO uint32_t STA;
    __IO uint32_t DMAADR;
    __IO uint32_t ADDATA;
    __IO uint32_t DADATA;
    __IO uint32_t DATCNT;
} ADKEY_TypeDef;

/**
  * @brief CRC
  */
typedef struct {
    __IO uint32_t CRC_CFG;                        // 0x0c
    __IO uint32_t CRC_INIT;                       // 0x04
    __IO uint32_t CRC_INV;                        // 0x08
    __IO uint32_t CRC_POLY;                       // 0x0c
    __IO uint32_t CRC_KST;                        // 0x10
    __IO uint32_t CRC_STA;                        // 0x14
         uint32_t RESERVED0;
    __IO uint32_t DMA_ADDR;                       // 0x1c
    __IO uint32_t DMA_LEN;                        // 0x20
    __IO uint32_t CRC_OUT;                        // 0x24
} CRC_TypeDef;


/**
  * @brief SYS_CTRL
  */
typedef struct
{
    __IO uint32_t SYS_KEY;
    __IO uint32_t SYS_CON0;
    __IO uint32_t SYS_CON1;
    __IO uint32_t SYS_CON2;
    __IO uint32_t SYS_CON3;
    __IO uint32_t SYS_CON4;
    __IO uint32_t SYS_CON5;
    __IO uint32_t SYS_CON6;
    __IO uint32_t SYS_CON7;
    __IO uint32_t CLK_CON0;
    __IO uint32_t CLK_CON1;
    __IO uint32_t CLK_CON2;
    __IO uint32_t CLK_CON3;
    __IO uint32_t CLK_CON4;
    __IO uint32_t CLK_CON5;
    __IO uint32_t CLK_CON6;
    __IO uint32_t CLK_CON7;
    __IO uint32_t HOSC_MNT;
    __IO uint32_t SYS_ERR0;
    __IO uint32_t WKUP_CON0;
    __IO uint32_t LP_CON0;
    __IO uint32_t MBIST_CON0;
    __IO uint32_t MBIST_MISR;
    __IO uint32_t CHIP_IDCN;
    __IO uint32_t MODE_REG;
    __IO uint32_t PMU_CON0;
    __IO uint32_t RPCON;
         uint32_t RESERVED0[(0x780-0x68-4)/4];
    __IO uint32_t FLS_NVR00;
    __IO uint32_t FLS_NVR04;
         uint32_t RESERVED1[3];
    __IO uint32_t FLS_NVR14;
         uint32_t RESERVED2[3];
    __IO uint32_t FLS_NVR24;
         uint32_t RESERVED3[(0x7c0-0x7a4-4)/4];
    __IO uint32_t FLS_MAIN10;
} SYSCTRL_TypeDef;

#define     SYSCTRL_REG_OPT(expression)       {SYSCTRL->SYS_KEY = 0x3fac87e4; expression; SYSCTRL->SYS_KEY = 0;}


/**
  * @brief GPIO controller
  */
typedef struct
{
    __IO uint32_t MODE;
    __IO uint32_t OTYPE;
    __IO uint32_t OSPEEDL;
    __IO uint32_t OSPEEDH;
    __IO uint32_t PUPD;
    __IO uint32_t IDAT;
    __IO uint32_t ODAT;
    __IO uint32_t BSR;
    __IO uint32_t LCK;
    __IO uint32_t AFR[2];
    __IO uint32_t TGL;
    __IO uint32_t IMK;
} GPIO_TypeDef;

/**
  * @brief DIV controller
  */
typedef struct
{
    __IO uint32_t DVDR;
    __IO uint32_t DVSR;
    __IO uint32_t DVQUO;
    __IO uint32_t DVREM;
    __IO uint32_t SR;
    __IO uint32_t DVCON;
} DIV_TypeDef;


/**
  * @brief SQRT controller
  */
typedef struct
{
    __IO uint32_t SQRT_IN;
} SQRT_TypeDef;

/**
  * @brief eFlash
  */
typedef struct {
    __IO uint32_t CTRLR0;               /*!< EFLASH control register,                     RW,  Address offset: 0x00           */
    __IO uint32_t KST;                  /*!< EFLASH kick start register,                  RO,  Address offset: 0x04           */
    __IO uint32_t DONE;                 /*!< EFLASH finish flag register,                 RO,  Address offset: 0x08           */
    __IO uint32_t RESERVED0;            /*!< EFLASH reserved0,                            RO,  Address offset: 0x0c           */
    __IO uint32_t PROG_ADDR;            /*!< EFLASH program address register,             RW,  Address offset: 0x10           */
    __IO uint32_t PROG_BYTE;            /*!< EFLASH program byte register,                RW,  Address offset: 0x14           */
    __IO uint32_t PROG_DATA;            /*!< EFLASH program data register,                RW,  Address offset: 0x18           */
         uint32_t RESERVED1;            /*!< EFLASH reserve1,                             RO,  Address offset: 0x1c           */
    __IO uint32_t ERASE_CTRL;           /*!< EFLASH erase register,                       R/W, Address offset: 0x20           */
         uint32_t RESERVED2[3];         /*!< EFLASH reserve2,                             RO,  Address offset: 0x24/0x28/0x2c */
    __IO uint32_t TIME_REG0;            /*!< EFLASH time register0,                       RW,  Address offset: 0x30           */
    __IO uint32_t TIME_REG1;            /*!< EFLASH time register1,                       RW,  Address offset: 0x34           */
    __IO uint32_t TIME_REG2;            /*!< EFLASH time register2,                       RW,  Address offset: 0x38           */
    __IO uint32_t TIME_REG3;            /*!< EFLASH time register3,                       RW,  Address offset: 0x3c           */
         uint32_t RESERVED3[4];         /*!< EFLASH reserve5,                             RO,  Address offset: 0x40-0x4c      */
    __IO uint32_t NVR_PASSWORD;         /*!< EFLASH NVR password register,                RW,  Address offset: 0x50           */
    __IO uint32_t MAIN_PASSWORD;        /*!< EFLASH MAIN password register,               RW,  Address offset: 0x54           */
    __IO uint32_t CRC_ADDR;             /*!< EFLASH CRC DMA address register,             RW,  Address offset: 0x58  */
    __IO uint32_t CRC_LEN;              /*!< EFLASH CRC DMA length register,              RW,  Address offset: 0x5c  */    
    __IO uint32_t CRC_OUT;              /*!< EFLASH CRC OUT register,                     RW,  Address offset: 0x60  */
         uint32_t RESERVED4[3];         /*!< EFLASH reserve9,                             RO,  Address offset: 0x64-0x6c  */
    __IO uint32_t MODE_STA;             /*!< EFLASH mode status register,                 RO,  Address offset: 0x70  */
    __IO uint32_t PERMISSION0;          /*!< EFLASH NVR Hardware control permission,      RO,  Address offset: 0x74  */
    __IO uint32_t PERMISSION1;          /*!< EFLASH MAIN Hardware control permission,     RO,  Address offset: 0x78  */
    __IO uint32_t CFG_SECTOR;           /*!< EFLASH MAIN User configuration sector,       RO,  Address offset: 0x7c  */
} EFLASH_TypeDef;

/**
  * @brief Comparator controller
  */
typedef struct
{
    __IO uint32_t CON;
    __IO uint32_t CON1;
    __IO uint32_t STA;
    __IO uint32_t CLR;    
} COMP_TypeDef;

/**
  * @brief DAC controller
  */
typedef struct
{
    __IO uint32_t CON;  
} DAC_TypeDef;

/**
  * @brief OPAM controller
  */
typedef struct
{
    __IO uint32_t CON;  
} OPAM_TypeDef;

/**
  * @brief touchkey controller
  */
typedef struct{
    __IO uint32_t TK_OFFSET0;
    __IO uint32_t TK_OFFSET1;
    __IO uint32_t TK_OFFSET2;
    __IO uint32_t TK_OFFSET3;
    __IO uint32_t TK_OFFSET4;
    __IO uint32_t TK_OFFSET5;
    __IO uint32_t TK_OFFSET6;
    __IO uint32_t TK_OFFSET7;
    __IO uint32_t TK_OFFSET8;
    __IO uint32_t TK_OFFSET9;
    __IO uint32_t TK_STBTHR;
    __IO uint32_t SAMPCON;
    __IO uint32_t TKSPTIM;
    __IO uint32_t TKKEYEN;
    __IO uint32_t TKIE;
    __IO uint32_t TKCON;
    __IO uint32_t INTPND;
    __IO uint32_t KEYPND;
    __IO uint32_t SCOVPND;
    __IO uint32_t SCDOPND;
    __IO uint32_t SAMPVAL;
    __IO uint32_t FILTVAL;
    __IO uint32_t KEYRDY;
    __IO uint32_t KEYSTA;
    __IO uint32_t TK_BADR;
    __IO uint32_t TK_BASEVAL;
    __IO uint32_t TK_ANACON0;
    __IO uint32_t TK_NOISETHR;
    __IO uint32_t TK_NOISETHRLT;
    __IO uint32_t TK_NOISETHRSEL;
    __IO uint32_t TK_ANAFRQCON0;
    __IO uint32_t TK_ANAFRQCON1;
    __IO uint32_t TK_ANAFRQCON2;
    __IO uint32_t TK_ANAFRQCON3;
}TK_TypeDef;

typedef struct{
    __IO uint32_t LED_CON0; 
    __IO uint32_t LED_CON1;
    __IO uint32_t LED_CON2;        
    __IO uint32_t LED_BADR;
}LED_TypeDef;

typedef struct{
    __IO uint32_t LVD_CON;
} LVD_TypeDef; 
/** 
  * @biref fadc
  */
/*
typedef struct {
    __IO uint32_t   FADCCON0        ;// 0x00
//    __IO uint32_t   FADCACSCON      ;// 0x04
//    __IO uint32_t   FADCACSDAT      ;// 0x08
    __IO uint32_t   FADCINT0        ;// 0x04
    __IO uint32_t   FADCFLAG        ;// 0x08
    __IO uint32_t   FADCDCOFFSET0   ;// 0x0c
    __IO uint32_t   FADCDCOFFSET1   ;// 0x10
    __IO uint32_t   FADCDMACON0     ;// 0x14
    __IO uint32_t   FADCDMACON1     ;// 0x18
    __IO uint32_t   FADCDMACON2     ;// 0x1c
    __IO uint32_t   FADCDMACON3     ;// 0x20
    __IO uint32_t   FADCDMACON4     ;// 0x24
    __IO uint32_t   FADCDMACON5     ;// 0x28
    __IO uint32_t   FADCDMACON6     ;// 0x2c
    __IO uint32_t   FADCDMACON7     ;// 0x30
    __IO uint32_t   FADCPPROC1CON0  ;// 0x34
    __IO uint32_t   FADCPPROC1CON1  ;// 0x38
    __IO uint32_t   FADCPPROC1CON2  ;// 0x3c
    __IO uint32_t   FADCPPROC1CON3  ;// 0x40
    __IO uint32_t   FADCPPROC1CON4  ;// 0x44
    __IO uint32_t   FADCPPROC1CON5  ;// 0x48
    __IO uint32_t   FADCPPROC1CON6  ;// 0x4c
    __IO uint32_t   FADCPPROC1CON7  ;// 0x50
    __IO uint32_t   FADCRES0        ;// 0x54
    __IO uint32_t   FADCRES1        ;// 0x58
    __IO uint32_t   FADCRES2        ;// 0x5c
    __IO uint32_t   FADCRES3        ;// 0x60
    __IO uint32_t   FADCSFRANACON0  ;// 0x64
    __IO uint32_t   FADCSFRANACON1  ;// 0x68   
    __IO uint32_t   FADCSFRADCCON0  ;// 0x6c   
    __IO uint32_t   FADCSFRSOCCON0  ;// 0x70   
    __IO uint32_t   FADCSFRSOCCON1  ;// 0x74   
    __IO uint32_t   FADCSFRSOCCON2  ;// 0x78   
    __IO uint32_t   FADCSFRSOCFLAG  ;// 0x7c   
    __IO uint32_t   FADCSFRCALIB0   ;// 0x80   
    __IO uint32_t   FADCSFRCALIB1   ;// 0x84   
    __IO uint32_t   FADCSFRWCOEF0   ;// 0x88   
    __IO uint32_t   FADCSFRWCOEF1   ;// 0x8c   
    __IO uint32_t   FADCSFRWCOEF2   ;// 0x90   
    __IO uint32_t   FADCSFRWCOEF3   ;// 0x94   
    __IO uint32_t   FADCSFRWCOEF4   ;// 0x98   
    __IO uint32_t   FADCSFRWCOEF5   ;// 0x9c    
    __IO uint32_t   FADCSFRWCOEF6   ;// 0xa0    
    __IO uint32_t   FADCSFRWCOEF7   ;// 0xa4   
    __IO uint32_t   FADCSFRWCOEF8   ;// 0xa8   
    __IO uint32_t   FADCSFRWCOEF9   ;// 0xac   
    __IO uint32_t   FADCSFRWCOEF10  ;// 0xb0   
    __IO uint32_t   FADCSFRWCOEF11  ;// 0xb4   
    __IO uint32_t   FADCSFRWCOEF12  ;// 0xb8   
} FADC_TypeDef;  
*/

/**
  * @}
  */

/** @addtogroup Peripheral_memory_map
  * @{
  */
/*! FLASH base address in the alias region */
#define FLASH_BASE              ((uint32_t)0x00000000)
/*! SRAM base address in the alias region */
#define SRAM_BASE               ((uint32_t)0x20000000)
/*! Peripheral base address in the alias region */
#define PERIPH_BASE             ((uint32_t)0x40000000)

//--------------Peripheral memory map------------------//
#define APB0_BASE               PERIPH_BASE
#define APB1_BASE               (PERIPH_BASE + 0x10000)
#define MIX_BASE                (PERIPH_BASE + 0x20000)

//--------------APB0 bus peris map---------------------//
#define LVD_BASE                (APB0_BASE + 0x100)
#define ADKEY_BASE              (APB0_BASE + 0x200)
#define PLLFRAC_BASE            (APB0_BASE + 0x300)
#define WDT_BASE                (APB0_BASE + 0x1000)
#define TIMER0_BASE             (APB0_BASE + 0x1100)
#define TIMER1_BASE             (APB0_BASE + 0x1200)
#define TIMER2_BASE             (APB0_BASE + 0x1300)
#define TIMER3_BASE             (APB0_BASE + 0x1400)
#define TIMER5_BASE             (APB0_BASE + 0x1700)
//#define EPWM_BASE               (APB0_BASE + 0x1800)
#define CRC_BASE                (APB0_BASE + 0x2000)
#define EFLASH_BASE             (APB0_BASE + 0x3000)

#define UART0_BASE              (APB0_BASE + 0x4000)
#define UART1_BASE              (APB0_BASE + 0x4100)
//#define UART2_BASE              (APB0_BASE + 0x4200)
//#define UART3_BASE              (APB0_BASE + 0x4300)
#define SPI0_BASE               (APB0_BASE + 0x4400)
#define SPI1_BASE               (APB0_BASE + 0x4500)
//#define QEI_BASE                (APB0_BASE + 0x4600)

//#define FADC_BASE               (APB0_BASE + 0x6000)
#define PMU_BASE                (APB0_BASE + 0x9000)

//--------------APB1 bus peris map---------------------//
#define TK_BASE                 (APB1_BASE + 0x0000)
#define TIMER4_BASE             (APB1_BASE + 0x0100)
#define COMP_BASE               (APB1_BASE + 0x0200)
#define DAC_BASE                (APB1_BASE + 0x0220)
#define OPAM_BASE               (APB1_BASE + 0x0230)
#define LED_BASE                (APB1_BASE + 0x0300) 
#define IR_BASE                 (APB1_BASE + 0x0400)

//--------------MIX bus peris map---------------------//
#define SYSCTRL_BASE            (MIX_BASE + 0x0000)
#define DIV_BASE                (MIX_BASE + 0xa00)
#define SQRT_BASE               (MIX_BASE + 0xa20)
#define GPIOA_BASE              (MIX_BASE + 0xb00)
#define GPIOB_BASE              (MIX_BASE + 0xc00)
#define GPIOC_BASE              (MIX_BASE + 0xd00)
//#define MAC_BASE                (AHB_BASE + 0x7000)


/**
  * @}
  */

/** @addtogroup Peripheral_declaration
  * @{
  */
#define LVD                     ((LVD_TypeDef *) LVD_BASE)
#define ADKEY                   ((ADKEY_TypeDef *)ADKEY_BASE)
#define PLLFRAC                 ((FPLL_TypeDef *)PLLFRAC_BASE)
#define WDT                     ((WDT_TypeDef *) WDT_BASE)
#define TIMER0                  ((TIMER_TypeDef *) TIMER0_BASE)
#define TIMER1                  ((TIMER_TypeDef *) TIMER1_BASE)
#define TIMER2                  ((TIMER_TypeDef *) TIMER2_BASE)
#define TIMER3                  ((TIMER_TypeDef *) TIMER3_BASE)
#define TIMER4                  ((TIMER_TypeDef *) TIMER4_BASE)
#define TIMER5                  ((TIMER5_TypeDef *) TIMER5_BASE)
//#define ADVTMR                  ((ADVTMR_TypeDef *) ADVTMR_BASE)
//#define EPWM                    ((EPWM_TypeDef *) EPWM_BASE)
#define CRC                     ((CRC_TypeDef *) CRC_BASE)
#define EFLASH                  ((EFLASH_TypeDef *) EFLASH_BASE)
#define COMP                    ((COMP_TypeDef *) COMP_BASE)
#define DAC                     ((DAC_TypeDef *) DAC_BASE)
#define OPAM                    ((OPAM_TypeDef *) OPAM_BASE)
#define TK                      ((TK_TypeDef *) TK_BASE)
#define LED                     ((LED_TypeDef *) LED_BASE)
#define IR                      ((IR_TypeDef *) IR_BASE)
//#define IIC0                    ((IIC_TypeDef *) IIC0_BASE)
//#define TDMA                    ((TDMA_TypeDef *) TDMA_BASE)
#define UART0                   ((UART_TypeDef *) UART0_BASE)
#define UART1                   ((UART_TypeDef *) UART1_BASE)
//#define UART2                   ((UART_TypeDef *) UART2_BASE)
//#define UART3                   ((UART_TypeDef *) UART3_BASE)
//#define DBGPATH                 ((DBGPATH_TypeDef *) DBGPATH_BASE)
#define SPI0                    ((SPI_I2C_TypeDef *) SPI0_BASE)
#define SPI1                    ((SPI_I2C_TypeDef *) SPI1_BASE)
//#define QEI                     ((QEI_TypeDef *) QEI_BASE)
//#define RTC                     ((RTC_TypeDef *) RTC_BASE)
//#define RFSPI                   ((RFSPI_TypeDef *) RFSPI_BASE)
//#define DMAC                    ((DMAC_TypeDef *) DMAC_BASE)
//#define SDIO_S                  ((SDIO_SLAVE_TypeDef *) SDIO_SLAVE_BASE)
//#define SDHC                    ((SDIO_HOST_TypeDef *)  SDIO_HOST_BASE)
#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC                   ((GPIO_TypeDef *) GPIOC_BASE)
#define DIV                     ((DIV_TypeDef *) DIV_BASE)
#define SQRT                     ((SQRT_TypeDef *) SQRT_BASE)
#define SYSCTRL                 ((SYSCTRL_TypeDef *) SYSCTRL_BASE)
//#define FADC                    ((FADC_TypeDef    *)  FADC_BASE)
//#define MODEM                   ((MODEM_TypeDef *) MODEM_BASE)
/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

//#define BIT(a)                ((uint32_t)1<<(a))
#ifdef __cplusplus
}
#endif

#endif /* __TS32FX_H */

/**
  * @}
  */

  /**
  * @}
  */

/*************************** (C) COPYRIGHT 2018 TOPSYS ***** END OF FILE *****/
